1. Field of the Invention
The present invention relates to a frequency synthesizer mainly for use in radio communication devices or the like, in particular to a phase lock loop frequency synthesizer which can perform high speed changing of frequency.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional phase lock loop frequency synthesizer. In FIG. 1, reference numeral 201 means a voltage controlled oscillator (hereinafter referred to as VCO), 202 means a variable frequency divider to divide oscillation frequency of the VCO 201,203 is a reference frequency oscillator (reference oscillator), 204 is a variable frequency divider to divide oscillation frequency of the reference oscillator 203, 205 is a phase comparator into which output from the variable frequency dividers 202 and 204 are input, 206 is a charging pump circuit, and 207 is a loop filter.
A description will now be given of the operation. The phase comparator 205 compares phase of the output from the variable frequency divider 202 dividing an output signal of the VCO 201 by N with phase of the output from the variable frequency divider 204 dividing a reference signal from the reference frequency oscillator 203 by M so as to output the phase difference as a pulse signal. The charging pump circuit 206 converts the pulse signal into an analog value. The phase difference signal passes through the loop filter 207 defining a characteristic of the loop, and thereafter serves as control voltage for the VCO 201. The VCO 201 generates an output signal having frequency corresponding to the control voltage. In such a way, control is made to reduce the phase difference between two divided frequencies so as to perform phase lock. The output signal serves as output of the frequency synthesizer, and is fed into the variable frequency divider 202. In a stationary state, output frequency of the frequency synthesizer is N times output frequency of the variable frequency divider 204. Further, the two divided frequencies are in phase with each other, and frequency stability of the VCO 201 is maintained to be identical with frequency stability of the reference frequency oscillator 203.
In case the frequency synthesizer is applied to a radio communication device or the like, it is necessary to change the frequency at a high speed. In many techniques to realize the high speed changing, the inventor has been disclosed an available technique in Japanese Patent Application Laid-Open No. 4-047812(1992), that is, has been disclosed the loop filter 207 having a configuration as shown in FIG. 2.
In FIG. 2, reference numeral 301 means an input terminal of the loop filter 207, 302 means an output terminal, 303 is a loop filter, 304 is another loop filter, 305 is still another loop filter, 3031 and 3032 are resistors serving as components of the loop filter 303, 3033 is a capacitor serving as the component of the loop filter 303, 3041and 3042 are resistors serving as components of the loop filter 304, and 3043 is a capacitor serving as the component of the loop filter 304.
Further, reference numerals 3051 and 3052 mean resistors serving as the components of the loop filter 305, 3053 means a capacitor serving as the component of the loop filter 305, reference numerals 307 to 315 are switches, and 316 is a voltage follower amplifier having high input impedance. In addition, FIG. 3 is a timing diagram showing a signal condition and a mode of each circuit portion corresponding to frequency changing process in the loop filter 207.
A description will now be given of the operation. In a phase lock loop (hereinafter referred to as PLL) employing a lag-lead type of loop filter as shown in FIG. 2, a loop gain K, natural angular frequency .omega.n, and a damping factor .zeta. can be expressed as follows: EQU K=Kv.multidot.K.phi./N EQU .omega.n=K/(.tau..sub.1 +.tau..sub.2) EQU .zeta.=(.omega.n/2){(1/K)+.tau..sub.2 }
where
Kv: sensitivity of the VCO PA1 K.phi.: sensitivity of the phase comparator PA1 N: the dividing number of the frequency divider, and EQU .tau..sub.1 =R.sub.1 C, .tau..sub.2 =R.sub.2 C
Next, when a step frequency variation of .DELTA.f occurs in the PLL, a frequency and phase drawing time (a loop response time) T is expressed by the sum of a frequency lock time ts and a phase lock time tp as follows (V. Manassewitsch "Frequency Synthesizers Theory and Design" Chap. 5, John Wiley and Sons, Inc., 1987): EQU T.apprxeq.ts+tp
In the expression, EQU ts=4(.DELTA.f/N).sup.2 /Bn.sup.3
where Bn is a noise band, and Bn can be expressed as follows: EQU Bn=(.omega.n/2){.zeta.+(1/4.zeta.)}
Further, EQU tp=(2/K.about.cos .epsilon..sub.ss).multidot.log.sub.e (2/.gamma..sub.lock)
where .epsilon..sub.ss is .DELTA..omega./K, and .gamma..sub.lock is a stable phase error. As will be obvious from the facts, the loop gain K, and .tau..sub.1, .tau..sub.2 may be appropriately switched in order to effectively reduce the frequency and phase drawing time (the loop response time).
A description will now be given of a technique to cause the loop gain and .tau..sub.1, .tau..sub.2 serving as loop time constants to be switched over at a time of frequency changing. A loop filter portion shown in FIG. 2 includes three loop filters 303, 304, and 305. At the time of frequency changing, in the first step, a dividing ratio M.sub.1 is used for the variable frequency divider 204 and a dividing ratio N.sub.1 is used for the variable frequency divider 202. In the second step, a dividing ratio M.sub.2 is used for the variable frequency divider 204 and a dividing ratio N.sub.2 is used for the variable frequency divider 202, and in the third step, dividing ratios M.sub.3 and N.sub.3 are used.
The loop filter 303 corresponds to the dividing ratios N.sub.1, M.sub.1, and is set to have appropriate values of .tau..sub.11, .tau..sub.12. Further, the loop filter 304 corresponds to the dividing ratios N.sub.2, M.sub.2, and is set to have appropriate loop time constants of .tau..sub.21, .tau..sub.22.
In addition, the loop filter 305 corresponds to the diving ratios N.sub.3, M.sub.3, and is set to have appropriate loop time constants of .tau..sub.31, .tau..sub.32. Further, the loop filter 305 is provided with a low pass filter to damp a spurious output, and in the low pass filter, resistance of resistors 3054, 3056 and capacitance of capacitors 3055, 3057 are determined so as to optimize a characteristic at a stationary time.
Next, a description will now be given of the operation at the time of frequency changing. First, the PLL is set to have the dividing ratios of N.sub.3 and M.sub.3, and is in the stationary state for frequency f.sub.0. In this condition, the switch 314 is in an ON state, and the switches 307 and 312 are in an OFF state. Therefore, the loop filter 305 is operated, and the capacitors in the loop filters 303,304 are charged to follow an output from the loop filter 305, that is, a value equivalent to the control voltage of the VCO 201.
At the same time of setting the dividing ratios N.sub.1 and M.sub.1, the switch 307 is turned ON and the switch 304 is turned OFF, and the switch 312 is left OFF. In this step, the loop filter 303 is operated, and the capacitors in the loop filters 304, 305 are charged by the voltage follower amplifier 316 to follow a variation in the control voltage of the VCO 201. At this time, .tau..sub.1 =R.sub.3031 .multidot.C.sub.3033 and .tau..sub.2 =R.sub.3032 .multidot.C.sub.3033 are determined so as to have appropriate values for the dividing ratios N.sub.1, M.sub.1, and converge at the frequency f.sub.1 in a short convergence time. A time required for the convergence is defined as .tau..sub.1.
Subsequently, at the same time of setting the dividing ratios N.sub.2 and M.sub.2, the switch 312 is turned ON and the switch 307 is turned OFF, and the switch 314 is left OFF. In this step, the loop filter 304 is operated, and the capacitors in the loop filters 303, 305 are charged by the voltage follower amplifier 316 to follow the variation in the control voltage of the VCO 201. At this time, .tau..sub.1 =R.sub.3041 .multidot.C.sub.3043 and .tau..sub.2 =R.sub.3042 .multidot.C.sub.3043 are determined so as to have appropriate values for the dividing ratios N.sub.2, M.sub.2, and converge at frequency f.sub.2 in a short convergence time. A time required for the convergence is defined as t.sub.2.
Next, at the same time of setting the dividing ratios N.sub.3 and M.sub.3, the switch 314 is turned ON and the switch 312 is turned OFF, and the switch 307 is left OFF. In this step, the loop filter 305 is operated, and the capacitors in the loop filters 303,304 are charged by the voltage follower amplifier 316 to follow the variation in the control voltage of the VCO 201. At this time, .tau..sub.1 =R.sub.3051 .multidot.C.sub.3053 and .tau..sub.2 =R.sub.3052 .multidot.C.sub.3053 are determined so as to have appropriate noise bands for the dividing ratios N.sub.3, M.sub.3 in the stationary state. Further, the loop filter 305 incudes the low pass filter having R.sub.3054, C.sub.3053, R.sub.3056, and C.sub.3057 in order to provide an appropriate spurious attenuation, resulting in an appropriate stationary state. A time period required for convergence from the frequency f.sub.2 to the frequency f.sub.3 is defined as t.sub.3.
As a result, t.sub.1 +t.sub.2 +t.sub.3 is obtained as a frequency changing time from the frequency f.sub.0 to the frequency f.sub.3, and is greatly improved as compared with a case of changing by using the frequency dividing ratios N.sub.3, M.sub.3 exclusively. FIG. 3 shows a timing diagram illustrating the changing process.
As set forth above, in the phase lock loop frequency synthesizer which has been disclosed by the inventor, it is possible to reduce the frequency changing time, and perform a sufficiently high speed operation. However, in the boundaries between the first step and the second step and between the second step and the third step of frequency changing, there are respectively errors for the target frequencies f.sub.2, f.sub.3 so that a time to draw the frequency is necessary. Hence, in the above configuration, there is a limitation in reduction of the entire frequency changing time.